Combinational Circuits

Designing combinational logic circuits with C/C++ language using the HLS approach

Understanding the basic concepts of High-Level Synthesis (HLS)

Using HLS concepts for designing combinational logic circuits

HLS design flow for FPGAs

Working with Xilinx Vivado-HLS and Vivado suite Toolsets

How to generate RTL hardware IPs using Vivado-HLS

Writing C-testbench in HLS

Implementing two exciting projects with HLS

Understanding the basic concepts of C/C++ coding

g., AND, OR, XOR, SHIFT )

BASYS3 evaluation board

Xilinx Vivado-HLS and Vivado ( Vivado HLx 2019.2: WebPACK and Editions for Windows or Linux)

This course is an elementary introduction to high-level synthesis (HLS) design flow. The target of the course is describing, debugging and implementing combinational logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog).

It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. This course is the first of its kind that builds the HLS design flow and skills along with the digital logic circuit concepts from scratch. Along the course, you will follow several examples describing the HLS concepts and techniques. The course contains numerous quizzes and exercises for you to practice and master the proposed methods and approaches.

This course is the first of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on combinational circuits, the other courses in the series will explain how to use HLS in designing sequential logic circuits, algorithm acceleration, and hybrid CPU+ FPGA heterogeneous systems.

Hardware eeers

Software eeers who are interested in FPGAs

Lecturers, researchers, professors who want to use FPGA-based HLS in lectures, courses or research

Digital Logic enthusiasts



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